Design Parameters for a Bit-Synchronized Transmission System

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dc.contributor.authorKundaeli, Herald N.
dc.date.accessioned2016-09-29T14:52:25Z
dc.date.available2016-09-29T14:52:25Z
dc.date.issued1993
dc.descriptionFull text can be accessed at http://www.tandfonline.com/doi/abs/10.1080/00207219308907118en_US
dc.description.abstractThe transmission reliability of transmission systems that employ synchronization codes For frame synchronization has been analysed in a previous report (Kundaeli 1991) in which it was shown that the introduction of verify states in the synchronization recovery and loss paths of the receiver resulted in increased reliability. Here we extend that analysis to provide a general method for determining the receiver design and performance parameters. We first derive the synchronization efficiency as a new performance parameter, then the applicable number of verify states for a receiver for practical ranges of both the channel error-rate and frame length.en_US
dc.identifier.citationKundaeli, H.N., 1993. Design parameters for a bit-synchronized transmission system. International Journal of Electronics Theoretical and Experimental, 75(3), pp.393-405.en_US
dc.identifier.doi10.1080/00207219308907118
dc.identifier.urihttp://hdl.handle.net/20.500.11810/4319
dc.language.isoenen_US
dc.publisherTaylor & Francisen_US
dc.titleDesign Parameters for a Bit-Synchronized Transmission Systemen_US
dc.typeJournal Article, Peer Revieweden_US
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